1. Field of the Invention
The present invention relates to a video signal processing device for obtaining a display video signal according to a synchronizing signal different from that for an input video signal. The video signal processing device writes an input video signal into a memory according to a write clock based on a synchronizing signal and reads a video signal from a memory according to a read clock based on a different synchronizing signal. In particular, the present invention relates to solution for problems stemming from a difference between write and read clocks.
2. Description of the Prior Art
With the development of personal computers, video signals in various display systems, such as the VAG standard (480 scanning lines/sec., approx. 60 frames/sec., non-interlace), have been utilized in addition to extant systems, such as the NTSC standard (525 scanning lines, 30 frames/sec., 60 fields/sec., interlace). The use of a variety of display systems for various video signals causes situations where video signal input in some systems (an input video signal) is read as a display video signal in a different system. In such a case, an input video signal must be converted into the system of a display video signal.
For this purpose, a field memory M, or the like, is provided so that an input video signal is written thereto, as shown in FIG. 1. A video signal supplied to the memory M is controlled by various signals from an input video clock generator 1. Receiving a horizontal synchronizing signal (an input H) and a vertical synchronizing signal (an input V) of an input video signal, the input video clock generator 1 outputs a write clock (WCLK), a write address reset signal (WRST), and a write enabling signal (WE) to the field memory M in synchronism with the input H and V. The field memory M, including a write counter, successively counts addresses of the write counter in response to the various clocks received, whereby an input video signal is written into the field memory M for every field.
On the other hand, a display video signal is read from the field memory M in response to various signals from a display video clock generator 2. Receiving a horizontal synchronizing signal (a display H) and a vertical synchronizing signal (a display V) of a display video signal, the display video clock generator 2 outputs a read clock (RCLK), a read address reset signal (RRST), and a read enabling signal (WE) to the field memory M. The field memory M, including a read counter as well, successively counts up addresses of the read counter so that a display video signal is read from the field memory M.
In this device, since display H and V signals can be arranged as desired, an input video signal can be converted into a display video signal synchronous to the input video signal. Note that a frame memory may be employed as a memory in lieu of a field memory.
In this arrangement, if a frame frequency of an input signal is higher than that of a display picture device (that is, a WCLK is faster than a RCLK), a write address may pass by a read address in a memory. If such a pass-by occurs within one memory (a frame memory, or the like), a display video signal read from memory after the pass-by is video data regarding the next frame, i.e. behind frame in terms of time. Displaying such display data intact will result in displaying video data in which a frame is switched into a different frame within a single frame period, which causes significant degrading of display quality.
On the other hand, in cases where a read address passes by a write address, a display video signal read from the memory after the pass-by is video data regarding the prior frame, i.e. ahead frame in terms of time, thus, display video data in which a frame is switched into a different frame ahead within a single scene frame period, resulting in degradation of display quality similar above.
In order to solve the above problem, it has been proposed to constantly observe write and read addresses so as to prohibit writing of video data for the frame to the memory, if it is detected that a pass-by will occur at some frame period.
According to this method, when a write address of a prior frame is passing by a read address of the next frame, the video signal for the next frame is not written into a memory. Instead, the video signal for one frame is discarded to thereby prevent occurrence of a pass-by. As a result, although a video signal for one frame is omitted in displaying, degrading of display quality within one scene can be prevented.
In cases, similar to the above, where a read address is about to pass by a write address of the next frame, a video signal for the next frame is not written into a memory. Instead, the video signal for the next frame is discarded, and the prior frame is repeatedly displayed. A writing operation is resumed from the video signal for a frame subsequent to the discarded frame, and a reading operation is accordingly resumed from that frame. As a result, although the discarded frame is not displayed, and the same frame is repeated, degrading of display quality within one frame period can be prevented.
For the above process of stopping a writing operation, however, read and write addresses must be constantly observed so as to predict whether or not a pass-by will occur until the start of a reading/writing operation of a video signal for a frame for which read and write addresses become the same. Further, if a frame frequency of an input video signal varies within a wide range, a large circuit is required for execution of comparison between read and write addresses and the above prediction.